1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a dynamic random access memory (DRAM) and a method of manufacturing the same.
2. Description of the Background Art
A demand for semiconductor memory devices is rapidly increasing as information equipments such as computers have come to be widely used. Functionally, devices having large storage capacity and capable of high speed operation are in great demand. Correspondingly, technique has been developed for improving degree of integration, higher responsiveness and reliability of the semiconductor memory device.
DRAMs (Dynamic Random Access Memories) are well known as semiconductor memory devices which allow random input and output of storage information. In general, the DRAM includes a memory cell array which is a storage region storing a large number of storage information and a peripheral circuitry for external input and output.
FIG. 71 is a block diagram showing a structure of a conventional DRAM. Referring to FIG. 71, a DRAM 150 includes a memory cell array 151 storing data of storage information, a row and column address buffer 152 externally receiving an address signal which is used for selecting a memory cell forming a unit storage circuit, row and column decoders 153 and 154 decoding the address signal and thereby designating the memory cell, a sense refresh amplifier 155 amplifying and reading a signal stored in the designated memory cell, data-in and data-out buffers 156 and 157 for input and output of data, and a clock generator 158 generating a clock signal.
The memory cell array 151 which occupies a large area on the semiconductor chip is formed of a plurality of memory cells which are arranged in a matrix form and each are adapted to store the unit storage information. FIG. 72 is an equivalent circuit diagram showing the memory cells for four bits in the memory cell array 151. Referring to FIG. 72, each memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. The memory of the above structure is called a memory cell of one-transistor/one-capacitor type. Since the memory cell of this type has a simple structure, degree of integration of the memory cell array can be easily increased, so that they are widely used in DRAMs of a large capacity.
The memory cells of the DRAMs utilize several types of capacitors, which are distinguished from each other according to their structures. Among these, in a stacked type capacitor, a major portion of the capacitor is extended up to positions above a gate electrode and a field isolating film for increasing opposing areas of electrodes in the capacitor. This increases a capacitance of the capacitor. The stacked type capacitor having the above feature ensures a sufficient capacitor capacitance even if elements are miniaturized in accordance with high integration of the semiconductor device. Consequently, the stacked type capacitors have been widely used in accordance with high integration of the semiconductor devices.
The semiconductor devices are now being improved to achieve higher degree of integration, and correspondingly the stacked type capacitors are now being developed. More specifically, in order to ensure sufficient capacitor capacitances required for storage operations of further miniaturized elements, there has been proposed a DRAM in which bit lines are buried and capacitor insulating films are formed of dielectric films, which are made of material having a high dielectric constant (referred to as "highly dielectric films" hereinafter).
FIG. 73 is a cross section showing the DRAM proposed in the prior art. In this DRAM, a silicon substrate 201 is provided at a predetermined region on its main surface with an element isolating oxide film 202 for isolating elements. The element isolating oxide film 202 surrounds a region in which source/drain regions 206a, 206b, 206c and 206d spaced by a predetermined distance are formed with channel regions 221 therebetween. Gate electrodes (word lines) 204b and 204c are formed on the channel regions 221 with a gate oxide film 205 therebetween. Word lines (gate electrodes) 204d and 204e are formed on the element isolating oxide film 202 with a predetermined space between each other.
The gate electrodes 204b, 204c, 204d and 204e are covered with an insulating film 207. The source/drain region 206a is electrically connected to a buried bit line 208, which is covered with an insulating film 209. An interlayer insulating film 210 having a flat surface is formed to cover the entire surface. The interlayer insulating film 210 is provided at predetermined regions with contact holes 210a. A polysilicon plug 211 which is electrically connected to the source/drain regions 206b, 206c or 206d is disposed in each contact hole 210a.
Adhesion layers 212 made of Ti are formed on the interlayer insulating film 210 and polysilicon plugs 211, and are electrically connected to the polysilicon plugs 211. Barrier layers 213 made of TiN are formed on the adhesion layers 212. Platinum layers 214 forming capacitor lower electrodes are formed on the barrier layers 213. The platinum layers 214 are covered with a highly dielectric film 215 which is made of SrTiO.sub.3 or the like and is formed on the platinum layers 214 and the interlayer insulating film 210. The highly dielectric film 215 is covered with a platinum layer 216 forming a capacitor upper electrode.
An interlayer insulating film 217 having a flat surface is formed on the platinum layer 216. Aluminum interconnections 218 are formed on the interlayer insulating film 217 with a predetermined space between each other. The aluminum interconnections 218 are covered with a protection film 219, on which an aluminum interconnection 220 is formed.
The platinum layer 214, highly dielectric film 215 and platinum layer 216 form a capacitor 250. The source/drain regions 206a and 206c and the gate electrode 204b form one of transfer gate transistors 203. The source/drain regions 206a and 206b and the gate electrode 204c form another one of transfer gate transistors 203.
The adhesion layers 212 are provided for the purpose of improving adhesion between the platinum layers 214 and the interlayer insulating film 210. The barrier layers 213 are provided for the purpose of preventing silicide reaction of the polysilicon plugs 211 and the platinum layers 214.
FIGS. 74-82 are cross sections showing a process for manufacturing the conventional DRAM shown in FIG. 73. The process for manufacturing the DRAM in the prior art will be described below.
As shown in FIG. 74, an element isolating oxide film 202 made of a silicon oxide film is formed in the predetermined region on the main surface of the silicon substrate 201 by an LOCOS (Local Oxidation of Silicon) method. Then, the gate oxide film 205 is formed, e.g., by thermal oxidation. The gate electrodes (word lines) 204b, 204c, 204d and 204e, which are made of polysilicon doped with a large amount of phosphorus, are selectively formed on the gate oxide film 205 and the element isolating oxide film 202. The insulating films 207 covering the gate electrodes 204b, 204c, 204d and 204e are formed. Ion implantation of impurity is carried out using the insulating films 207 as a mask to form the source/drain regions 206a, 206b, 206c and 206d.
A polysilicon layer is formed on the whole surface, and then is patterned into a predetermined configuration to form the buried bit line 208 which is in direct contact with the source/drain region 206a. The insulating film 209 covering the buried bit line 208 is formed. Thereafter, the interlayer insulating film 210 of about 5000 to 10000 .ANG. in thickness is formed on the whole surface by the CVD method.
As shown in FIG. 75, a resist 222 is formed in predetermined regions on the surface of the interlayer insulating film 210. Using the resist 222 as a mask, anisotropic etching is effected on the interlayer insulating film 210 to form the contact holes 210a as shown in FIG. 76.
As shown in FIG. 77, a polysilicon layer 211a of a predetermined thickness filling the contact holes 210a is formed on the interlayer insulating film 210. Etchback is effected on the polysilicon layer 211a to form the polysilicon plugs 211 as shown in FIG. 78.
As shown in FIG. 79, a titanium layer 212a, a TiN layer 213a and a platinum layer 214a are sequentially formed on the polysilicon plugs 211 and interlayer insulating film 210. A resist 223 is formed on predetermined regions 223 on the platinum layer 214a. Using the resist 223 as a mask, anisotropic etching is effected on the platinum layer 214a, TiN layer 213 and titanium layer 212a to form the adhesion layers 212, barrier layers 213 and platinum layers (i.e., capacitor lower electrodes) as shown in FIG. 80, respectively.
Then, as shown in FIG. 81, the high dielectric film 215 covering the platinum layers 214 is formed on the platinum layers 214 and interlayer insulating film 210 by the sputter method or the like. The highly dielectric film 215 is made of SrTiO.sub.3, Pb(Zr, Ti)O.sub.3 or the like. The platinum layer 216 forming the capacitor upper electrode is formed to cover the highly dielectric film 215 by the sputter method.
As shown in FIG. 82, the interlayer insulating film 217 covering the platinum layer 216 is formed by the CVD method. The aluminum interconnections 218, which correspond to the word lines 204b, 204c, 204d and 204e, respectively and are spaced by a predetermined distance from each other, are formed on the interlayer insulating film 217.
Finally, as shown in FIG. 73, the protection film 219 made of a silicon oxide film and covering the aluminum interconnections 218 are formed by the CVD method. The aluminum interconnection 220 is formed on the protection film 219. In this manner, the conventional DRAM is formed.
In the conventional DRAM shown in FIG. 73, the adhesion layer 212 made of Ti can achieve good adhesion between the interlayer insulating film 210 and the platinum layer 214 forming the capacitor lower electrode.
In the conventional structure, however, good adhesion cannot be obtained between the highly dielectric film 215 and the interlayer insulating film 210. This problem is peculiar to the case where the capacitor dielectric film is made of a material having a high dielectric constant and a high melting point. If the capacitor dielectric film is formed of a silicon oxide film or the like having a low dielectric constant, good adhesion is obtained between the capacitor dielectric film and the silicon oxide film disposed under the same, so that no problem is caused relating to the adhesion of the capacitor dielectric film. However, in the case where the capacitor dielectric film is formed of the highly dielectric film described above, a problem arises in connection with the adhesion between the capacitor dielectric film and the interlayer insulating film 210 made of the silicon oxide film and located under the same. If good adhesion is not obtained between the highly dielectric film 215, i.e., capacitor dielectric film and the interlayer insulating film 210, the high dielectric film 215 may be separated, resulting in reduction of the overall reliability of the capacitor.
In the conventional structure shown in FIG. 73, the adhesion layer 212 is interposed between the platinum layer 214 and the interlayer insulating film 210 for improving the adhesion between the platinum layer 214 and the interlayer insulating film 210. This unpreferably increases a difference in level at a stepped portion including the adhesion layer 212, barrier layer 213 and platinum layer 214.